library ieee;
use ieee.std_logic_1164.all;

entity TRIGGER is
    port(
        D,CLK,PSET,CLR: in std_logic;
        Q: out std_logic
    );
end TRIGGER;

architecture RTL of TRIGGER is
begin
    process(CLK,CLR)
    begin
        if CLR='0' then Q<='0';
        elsif CLK'event and CLK='1' then
            if PSET='0' then Q<='1';
            else Q<=D;
            end if;
        end if;
    end process;
end RTL;